1. Field
The invention relates to an electronic semiconductor package, an electronic arrangement and a method for manufacturing an electronic semiconductor package.
2. Description of the State of the Art
When package an electronic chip by means of an encapsulation structure, the electronic chip mounted on the electric carrier is cast with an encapsulating compound and thereby a surface region of the electrical carrier is kept free. A thermal interface structure (TIM, thermal interface material), which electrically decouples the electrical carrier with respect to its surroundings and couples it thermally with its surroundings, can then be mounted on one part of the encapsulation structure and the surface region of the electrical carrier. The user can then mount a heat dissipation element, for example in the form of a heat sink, on such an electronic semiconductor package, in order to be able to discharge accumulated waste heat from the electronic semiconductor package to the periphery during the operation of the electronic semiconductor package with the electronic chip (for example a power semiconductor chip).
With an undesirable delaminating of the thermal interface material from the encapsulation structure, disruptive leakage currents can form between the surroundings of the electronic semiconductor package and the electrical carrier coupled to an electronic chip, which affect the dielectric strength of the electronic semiconductor package.